The development of semiconductor technologies in recent years has been accompanied by serialization of data transmission between LSI devices. There are instances where the operating clock frequency of a transmit LSI device and that of a receive LSI device coincide and instances where they do not. One example of a method adopted in a case where these frequencies do not coincide is to reduce EMI (EletroMagnetic Interference) using a spread spectrum clock in which frequency modulation is applied in the transmit LSI device. A method of extracting a clock signal from frequency-modulated serial data in the receive LSI device relies upon a known clock and data recovery circuit of the kind shown in FIG. 13 (see “1.5 Gbps, 5150 ppm Spread Spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps Level Detector for Serial ATA”, Symposium on VLSI Circuits Digest of Technical Papers 5-3, FIG. 1, June/2002).
As shown in FIG. 13, the circuit includes a phase tracking loop constituted by a phase detector 201, an integrator 202 and a phase interpolator 206, and a frequency tracking loop constituted by an integrator 203, a charge pump 214, a loop filter 215, a VCO (voltage-controlled oscillator) 216 and the phase interpolator 206. Here a synchronizing clock signal is made to track data that has been frequency-modulated by a spread spectrum clock. Furthermore, in order to initialize the frequency of the VCO 216, the circuit includes a frequency initializing loop constituted by a phase frequency detector 211, the charge pump 212, loop filter 215 and VCO 216.
However, a clock and data recovery circuit having a construction that does not include the integrator 203, charge pump 214, loop filter 215 and VCO 216 constituting the frequency tracking loop in FIG. 13 finds difficulty in tracking the phase of serial data frequency-modulated by a spread spectrum clock. This will be explained below. In a case where the clock and data recovery circuit constructed by the phase detector 201, integrator 202 and phase interpolator 206 is such that the resolution of the phase interpolator 206 is 1/64 and the integrator 202 is constituted by an up-down counter that counts up and down to +4 and −4, tracking can be achieved only to a frequency difference of 1/(64×4)=0.39%. On the other hand, with a serial ATA system, tracking of frequency modulation on the order of, e.g., 0.5% is required.
A clock and data recovery circuit having the frequency tracking loop that includes the charge pump 214, loop filter 215 VCO 216 is capable of being constructed so as to track frequency modulation of 0.5% or greater. In a multichannel implementation, however, chip size and power consumption are great. Specifically, when a clock and data recovery circuit having a frequency tracking loop that includes a charge pump, loop filter and VCO has a multichannel configuration, the frequency tracking loop including the charge pump, loop filter and VCO is provided in all of the channels, resulting in a large chip size. Power consumption increases if a high-speed VCO is provided in all of the channels in a high-speed system of 1 Gbps or higher.
In an attempt to solve these problems, a clock and data recovery circuit of the kind shown for example in FIG. 10 has been proposed by the applicant in an earlier application (Japanese Patent Application No. 2003-166712; Japanese Patent Kokai Publication No. JP2005-005999A).
As shown in FIG. 10, the clock and data recovery circuit proposed in the earlier application (Japanese Patent Application No. 2003-166712; Japanese Patent Kokai Publication No. JP2005-005999A) includes a phase detector 101, integrators 102 and 103, a pattern generator 104, a mixer 105 and a phase interpolator 106. The circuit tracks frequency modulation by the action of a frequency tracking loop constructed by the integrator 102, pattern generator 104 and mixer 105, and tracks slight fluctuations in phase, which cannot be tracked by the frequency tracking loop, by the action of a phase tracking loop constructed by the integrator 103 and mixer 105. The mixer 105 is a circuit that mixes the results from the frequency and phase tracking loops. The mixer controls the phase of the phase interpolator 106, whereby a clock corresponding to serial data is extracted.
FIG. 11 is a diagram illustrating another implementation proposed in the earlier application (Japanese Patent Application No. 2003-166712). In this case, the integrators 102 and 103 of FIG. 10 are replaced by a single shared interpolator 102.
The present inventor has discovered that the characteristics of the clock and data recovery circuit disclosed in the earlier application (Japanese Patent Application No. 2003-166712) can be improved further by improving the jitter tolerance characteristic of a certain frequency band.
The frequency tracking loop exhibits an excellent tracking characteristic with regard to low-frequency jitter but does not respond to high-frequency jitter. The speed of response of the frequency tracking loop is low and there are instances where the phase interpolator 106 is controlled in the wrong direction with regard to jitter in a frequency band approximately midway between the high and low frequencies. In such cases there may be a decline in the jitter tolerance characteristic in a certain frequency band.
FIG. 12 illustrates the results of a simulation of jitter tolerance characteristic in a case where both the frequency tracking loop and phase tracking loop are made to operate and in a case, which is for comparison purposes, where only the phase tracking loop is made to operate. The simulation indicates an excellent jitter tolerance characteristic with respect to low-frequency jitter owing to the action of the frequency tracking loop in a case where both the frequency tracking loop and phase tracking loop are made to operate. Results approximately match with respect to high-frequency jitter. However, with regard to jitter of a frequency that is mid-range between the high and low frequencies, the simulation indicates that the jitter tolerance characteristic is degraded in a case where both the frequency and phase tracking loops are made to operate.